In a typical integrated circuit (IC) formation process, a passivation layer or passivation layers are formed to protect the internal semiconductor devices after the completion of metallization. The passivation layers are typically formed with deposition of an oxide layer and a nitride layer. In some examples, the oxide layer and the nitride layer are formed by performing plasma enhanced chemical vapor deposition (PECVD).
However, the conventional passivation layers have a number of shortcomings. With the trend of high integration of semiconductor devices, the distance between the metallization layers decreases. The PECVD oxide layer and the PECVD nitride layer can not sufficiently fill in the gap between the metallization layers due to their characteristic of step coverage, thereby voids would be formed. The voids would weaken mechanical protection for the underlying semiconductor devices. Some contamination or moisture can penetrate through the semiconductor devices. Also, the electrical performances of the semiconductor devices would be negatively affected. Therefore, the failure rate of the overall assembly could increase.
Accordingly, there is a need for an improved structure and method for fabricating the passivation layer.